Subject: [sv-bc] Back annotation of interfaces proposal
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Fri Mar 14 2003 - 08:10:42 PST
ADD to draft 3 a new section 18.2.4
18.2.4 Back annotation
When the interfaces are expanded out into individual wires, the ports need
to be given legal identifiers. A synthesis or layout tool shall use the
escaped version of the hierarchical name. For example
module memMod ( \a.req, \a.gnt, \a.addr, \a.data, \a.mode, \a.start,
\a.rdy, clk);
These names can then be used in an SDF file for back annotation.
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