Subject: Re: [sv-bc] SV-BC75: variables in unnamed blocks
From: Dave Rich (David.Rich@synopsys.com)
Date: Thu Mar 06 2003 - 23:59:31 PST
OK, I'll remove the last sentence.
Would this wording be clearer:
"Note that in SystemVerilog, data can be declared in unnamed blocks as
well as in named blocks. This data is visible to the unnamed block and
any nested blocks below it. References via hierarchical identifiers to
this data are not available."
Francoise Martinolle wrote:
> Dave,
>
> given the email feedback on this, I think this has to be reworded.
> In particular the sentence about hierarchical references is too vague.
> and we want to suppress the auto-generated scope name
>
> Disagree with the wording
> :
> WITH
> "Note that in SystemVerilog, data can be declared in unnamed blocks as
> well as in named blocks. This data is visible to the unnamed block and
> any nested blocks below it. Hierarchical references cannot be used to
> access this data by name. Some tools may automatically generate scope
> names for data in these unnamed blocks, however, these generated scope
> names shall not be visible to the scopes below it."
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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