[sv-bc] SV-BC 39: illgal modport declarations


Subject: [sv-bc] SV-BC 39: illgal modport declarations
From: Francoise Martinolle (fm@cadence.com)
Date: Thu Mar 06 2003 - 12:28:44 PST


Brad,
You may want to add some better comments in the interface examples:
I think there is also a typo.

Proposal --

In Section 18.4 on "Interfaces:Modports" (13.4 in the 3.0 LRM),
before the final sentence, add the following:

----------------------------------------------------------------------

All of the names used in a modport declaration shall be declared
by the same interface as is the modport itself. In particular,
the names used shall not be those declared by another enclosing interface,
and a modport declaration shall not implicitly declare new ports.
The following interface declarations would be illegal:

    interface i;
           wire x, y;
           interface illegal;
             wire a, b, c, d;
             // x, y not declared by the interface "illegal"
             modport master(input a, b, x, output c, d, y);
             modport slave(input a, b, x, output c, d, y);
           endinterface : illegal
           illegal ch1, ch2;
           modport master2 (chi.master, ch2.master); => typo? ch1?
    endinterface : i

    interface illegal;
            // a, b, c, d not declared by this interface
            modport master(input a, b, output c, d);
            modport slave(output a, b, output c, d);
    endinterface : illegal



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