Subject: [sv-bc] Re: extern modules
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Feb 28 2003 - 15:55:01 PST
I'd like to propose a minor change to the "extern module" syntax. If
"endmodule" is added
as in:
extern module <module name>(...); endmodule
- it's easier to extend the extern declaration to include internal
variables that are reachable
by hierarchical reference, e.g.:
extern module tran(inout gate,inout source,inout drain);
real temperature; // probable/writable
endmodule
This functionality is useful in an AMS context where analog models are
built into the
simulator and no full description is supplied. Adding ports for
non-electrical nodes
will confuse non-AMS aware tools. It may also be useful with pre-compiled IP
that wants to make some internals available to a testbench.
What is actually declarable inbetween the ";" and "endmodule" can be
left for later,
but leaving the syntax with ";" as the terminal will make future
extension awkward.
Regards,
Kev.
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