Subject: Re: [sv-bc] Proposal for extern modules
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Feb 19 2003 - 08:38:56 PST
> From: "Peter Flake" <Peter.Flake@synopsys.com>
>
> Steven,
>
> The problem with dummy modules is that you have to maintain two port lists,
> the real one and the dummy one.
>
> The extern module can be automatically checked against the real module or
> the real one can use the extern.
Do you mean like VHDL's entity/architecture?
If we added module inheritance you would be able to do that fairly easily:
virtual module foo (input a, output b); endmodule // entity (stub)
module bar extends foo; // inherit port-list from foo
wire a;
reg b;
...
endmodule
I use "virtual" rather than "extern" since that's the class syntax for
something non-instantiable.
Kev.
> Peter.
>
> At 14:28 18/02/2003 -0500, Steven Sharp wrote:
> >Karen,
> >
> >Like Adam, I don't understand why you can't use the actual module
> >declarations.
> >They are apparently available, since you mentioned using scripts to create
> >external declarations from them. And you proposed a .* syntax for the module
> >declaration to make it use the port list from the external declaration, again
> >implying that both were available.
> >
> >If there is some situation where the real module declaration isn't available,
> >you could always use a dummy module (AKA shell or stub). They look pretty
> >much like your extern declarations; just take the word "extern" off the front
> >and add the word "endmodule" to the end. And if the synthesis compiler needs
> >to know that these are dummy declarations, you can put the "extern" back on
> >as an attribute. Also, configs could be used to compile all of the stub
> >modules into a separate library if desired.
> >
> >Steven Sharp
> >sharp@cadence.com
>
>
>
>
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