Re: [sv-bc] email voting for several proposals


Subject: Re: [sv-bc] email voting for several proposals
From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Wed Feb 12 2003 - 07:43:38 PST


My votes are the same as Dave's.

Gord.

> Dave Rich wrote:
>
> My votes below
>
> Srouji, Johny wrote:
>
> > Hi All,
> >
> > There is a back log of existing proposals, which we have not been able to
> > vote on in committee. It is not expected that all of these to pass, but
> > it is desirable to get all of the changes we can all agree to in the
> > editorial process as soon as possible. Here is the process that we agreed
> > on, during our last F2F meeting, Jan 22nd:
> >
> > * Whoever does not vote, will be assumed as not objecting
> > * If an eligible voting member votes against it, the topic will be
> > brought up for a discussion
> >
> > The voting will close on by the end of next Tuesday, Feb 18th. .
> >
> >
> >
> > I have a couple of requests:
> >
> > * Please submit your vote below, as YES or NO. If you vote NO, please
> > come up w/ a counter proposal and/or modifications/reasons, and
> > submit it by Feb 25th
> > * It would be useful to get all votes (to be used as a straw poll, if
> > needed)
> >
> > Thanks,
> >
> > --- Johny.
> >
> >
> >
> >
> >
> > _X_yes __no SV-BC20 Typedef and generate issues
> > URL under: http://www.eda.org/sv-bc/hm/0061.html
> > __yes _X_no SV-BC21-1,2,3 Granularity issues and function
> > sensitivites
> >
> This needs a write-up that can be put into the LRM. Otherwise I am OK with
> the proposal
>
> > URL under: http://www.eda.org/sv-bc/hm/0292.html
> > _X_yes __no SV-BC29 Need bits to real and real to bits
> > URL under: http://www.eda.org/sv-bc/hm/0293.html
> > _X_yes __no SV-BC2 Time Precision and timescale
> > URL under: http://www.eda.org/sv-bc/hm/0326.html
> > _X_yes __no SV-BC58 Slices of unpacked arrays
> > URL under: http://www.eda.org/sv-bc/hm/0331.html
> > __yes _X_no SV-BC5 Data alignment and packing
> >
> Sharing C-compatible layouts with C code is beyond the charter of the SV-BC
>
> > URL under: http://www.eda.org/sv-bc/hm/0363.html
> >
> > _X_yes __no SV-BC10b-1 Mascarading descriptions for VCD
> > URL under: http://www.eda.org/sv-bc/hm/0380.html
> > _X_yes __no SV-BC62a Simpler declaration of unpacked struct
> > lits
> > URL under: http://www.eda.org/sv-bc/hm/0382.html
> > _X_yes __no SV-BC68 BNF Issues
> > URL under: http://www.eda.org/sv-bc/hm/0404.html
> > _X_yes __no SV-BC60 Modport syntax issues
> > URL under: http://www.eda.org/sv-bc/hm/0410.html
> > _X_yes __no SV-BC18h,i logic variable issues
> > URL under: http://www.eda.org/sv-bc/hm/0415.html
> > _X_yes __no SV-BC35 task port declarations in BNF
> > URL under: http://www.eda.org/sv-bc/hm/0417.html
> > _X_yes __no SV-BC8-5 Issues with time data type
> > SV-BC12 Constant exprs; difference among
> > decls
> > SV-BC16f Issue with extern forkjoin task
> > http://www.eda.org/sv-bc/hm/0422.html
> > _X_yes __no SV-BC66 Update BNF to reflect ETF changes
> > http://www.eda.org/sv-bc/hm/0433.html
> > _X_yes __no SV-BC45 Dynamic checking of enums is expensive
> > http://www.eda.org/sv-bc/hm/0434.html
> > _X_yes __no SV-BC67 () after interface instantiation needed
> > http://www.eda.org/sv-bc/hm/0435.html
> > __yes _X_no SV-BC65 Structure literals vs concat determination
> >
> I am going to have to change my terminology to be in line with BC-62a
>
> >
> > http://www.eda.org/sv-bc/hm/0436.html
> > _X_yes __no SV-BC35 Structure literals vs concat determination
> >
> This is not the correct subject line, but I still vote yes for this proposal
>
> >
> > http://www.eda.org/sv-bc/hm/0445.html
> > _X_yes __no SV-BC34a Multiple namespaces exist
> > http://www.eda.org/sv-bc/hm/0446.html
> > _X_yes __no SV-BC19-17a signed function declarations (BNF)
> > SV-BC62b Packed array of packed structs
> > http://www.eda.org/sv-bc/hm/0454.html
> >
> >
> >
> >
>
> --
> --
> Dave Rich
> Principal Engineer, CAE, VTG
> Tel: 650-584-4026
> Cell: 510-589-2625
> DaveR@Synopsys.com

-- 
----------------------------------------------------------------------
Gord Vreugdenhil                                 gvreugde@synopsys.com
Staff Engineer, VCS (Verification Tech. Group)   (503) 547-6054
Synopsys Inc., Beaverton OR



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