Subject: [sv-bc] Proposal for SV-BC-34A Namespaces
From: Dave Rich (David.Rich@synopsys.com)
Date: Sun Feb 09 2003 - 23:54:26 PST
Replace Section 12.9 with
SystemVerilog has five namespaces for identifiers. Verilog’s global
definitions name space collapses onto the module name space and exists
as the top-level scope, $root. Module, primitive, and interface
identifiers are local to the module name space where there are defined.
The five namespaces are described as follows:
1. The /text macro name space/ is global. Since text macro names are
introduced and used with a leading ‘ character, they remain
unambiguous with any other name space. The text macro names are
defined in the linear order of appearance in the set of input
files that make up the description of the design unit. Subsequent
definitions of the same name override the previous definitions for
the balance of the input files.
2. The /module name space/ is introduced by $root and the module,
macromodule, interface, and primitive constructs. It unifies the
definition of functions, tasks, named blocks, instance names,
parameters, named events, net type of declaration, variable type
of declaration and user defined types.
3. The /block name space/ is introduced by named or unnamed blocks,
the specify, function, and task constructs. It unifies the
definitions of the named blocks, functions, tasks, parameters,
named events, variable type of declaration and user defined types.
4. The /port name space/ is introduced by the module, macromodule,
interface, primitive, function, and task constructs. It provides a
means of structurally defining connections between two objects
that are in two different name spaces. The connection can be
unidirectional (either input or output) or bi-directional (inout).
The port name space overlaps the module and the block name spaces.
Essentially, the port name space specifies the type of connection
between names in different name spaces. The port type of
declarations includes input, output, and inout. A port name
introduced in the port name space may be reintroduced in the
module name space by declaring a variable or a wire with the same
name as the port name.
5. The /attribute name space/ is enclosed by the (* and *) constructs
attached to a language element (see 2.8). An attribute name can be
defined and used only in the attribute name space. Any other type
of name cannot be defined in this name space.
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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