Subject: [sv-bc] Re: SV-EC Proposal: Procedural Assignments to Declared or Implicit Wires - Correction
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Feb 03 2003 - 16:03:26 PST
At 11:21 AM 2/3/03 -0800, Clifford E. Cummings wrote:
>...
>There are two bigger problems that we have not addressed:
>
>(1) Making multiple RTL procedural assignments to the same variable in
>the same module. For simulation, you can get race-prone last assignment
>wins behavior by making procedural assignments to the same variable from
>two clocked always blocks, but synthesis tools like Synopsys will warn and
>then infer two flip-flops with the outputs anded together, which does not
>remotely behave the same as the pre-synthesis simulation. There have been
>no proposals to address the multi-procedural-block assignment problem,
>which I consider to be a much bigger problem than the multi-driver
>problem. I just give the guideline: do make RTL procedural assignments to
>the same variable from more than one procedural block.
Should have been: Guideline: Do NOT make RTL procedural assignments to the
same variable from more than one procedural block.
>(2) An RTL coder changes a procedural assignment to a continuous
>assignment within a module and forgets to change the declaration or vice
>versa. This is not a hard problem to fix, it is just such an annoying and
>common mistake and requiring changes to the declaration has no real value
>to the design. This is what I am trying to change with the following proposal.
...
Apologies for the confusion.
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
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