Subject: [sv-bc] SV-BC-35 - follow up
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Thu Jan 30 2003 - 04:04:45 PST
This E-maul refers to the E-mail send by Shalom
http://www.eda.org/vlog-pp/sv-bc/hm/0155.html
This issue involves two functional differences allowed between the Verilog
BNF and the
System-Verilog BNF.
1. In Verilog 2001 input and inout ports of a module must be of a net type.
The
System-Verilog BNF allows the use of nets, data type (e.g. bit, byte, logic,
real etc...),
events, and triregs.
2. In Verilog 2001 if a type of a task port or a function port is defined,
then the
defined type must be a variable (reg, integer, real, realtime, or time)
meaning the following declarations will be considered illegal :
task aTask;
input wire ain;
output trior aout;
inout trireg ainout;
input event adj;
...
endtask
The System-Verilog BNF enables the parsing of such declarations.
The Question is if these two changes were done on purpose ?
Do we want to support all data types as module input and inout ports ?
Do we want to support all data types and net types as function and task
ports ?
Once I receive an answer for the previous question I will try to propose a
change
to the BNF that will deal with these issues.
Thanks,
Danny
Dan Jacobi
Phone : (972)-4-8655855
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