Subject: Re: [sv-ec] Re: [sv-bc] Packed arrays
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Tue Jan 28 2003 - 13:20:11 PST
The issue was more one of did the SV-EC want to extend the language to
allow packed arrays
of reals, etc., rather than what the current state was.
Karen
At 12:24 PM 1/28/03 -0800, Arturo Salz wrote:
>The statement in section 4.2 is correct. This is what was discussed and
>agreed at the face-to-face BC meeting.
>
> Arturo
>----- Original Message -----
>From: <mailto:david.smith@synopsys.COM>David W. Smith
>To: <mailto:sv-ec@eda.org>sv-ec@eda.org
>Cc: <mailto:sv-bc@eda.org>sv-bc@eda.org
>Sent: Tuesday, January 28, 2003 11:31 AM
>Subject: [sv-bc] Packed arrays
>
>One of the questions that was asked by SV-BC (TRN-7) is whether packed
>arrays can accept reals and other non-integral types (strings, events,
>classes). The LRM states in Section 4.2 that "Packed arrays can only be
>made of the single bit types: bit, logic, reg, wire, and the other net types".
>
>Seems clear to me. Any comments?
>
>Regards
>David
>
>David W. Smith
>Synopsys Scientist
>Synopsys, Inc.
>Synopsys Technology Park
>2025 NW Cornelius Pass Road
>Hillsboro, OR 97124
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>
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