Subject: [sv-bc] Test and set operator in Chapter 9
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Jan 27 2003 - 11:57:12 PST
The 5th paragraph of section 9.1 creates a new requirement on the
simulation cycle that attempts to introduce an atomic test and set
operator. This came up in our sv-ec meetings.
Can we create this as a new sv-bc issue, to remove this sentence?
In general the ability to embed assignments in expressions does not
change the fact that a simulator may interupt during the assignment
statement.
In SV 3.1, if you want a test and set a semaphore can be used.
Jay
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Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
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