Subject: Re: packed arrays other than bit,logic,reg and wire
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Fri Jan 17 2003 - 06:57:32 PST
Dave,
This is to accommodate legacy Verilog which has
integer[31:0] i;
This means the same as logic signed [31:0], not 32 integers.
Peter.
At 11:35 16/01/2003 -0800, Dave Rich wrote:
>Here is another potential BNF error
>
>Section 4.2 says
>Packed arrays can only be made of the single bit types: bit, logic, reg,
>wire, and the other net types.
>
>However the BNF is in error and says you can pack integer type arrays also.
>OLD:
>A.2.2.1 Net and variable types
>data_type ::=
>integer_vector_type [ signing ] { packed_dimension } [ range ]
>| integer_atom_type [ signing ] { packed_dimension } <-- this is not allowed
>| type_declaration_identifier
>| non_integer_type
>| struct [ packed ] [ signing ] { { struct_union_member } }
>| union [ packed ] [ signing ] { { struct_union_member } }
>| enum [ integer_type [ signing ] { packed_dimension } ]
>{ enum_identifier [ = constant_expression ] { , enum_identifier [ =
>constant_expression ] } }
>| void
>
>NEW:
>A.2.2.1 Net and variable types
>data_type ::=
>integer_vector_type [ signing ] { packed_dimension } [ range ]
>| integer_atom_type [ signing ]
>| type_declaration_identifier
>| non_integer_type
>| struct [ packed ] [ signing ] { { struct_union_member } }
>| union [ packed ] [ signing ] { { struct_union_member } }
>| enum [ integer_type [ signing ] { packed_dimension } ]
>{ enum_identifier [ = constant_expression ] { , enum_identifier [ =
>constant_expression ] } }
>| void
>
>--
>--
>Dave Rich
>Principal Engineer, CAE, VTG
>Tel: 650-584-4026
>Cell: 510-589-2625
>DaveR@Synopsys.com
>
>
>
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