Subject: Re: More issues
From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Dec 11 2002 - 08:41:15 PST
issue a warning message
Hello All;
Steve wrote:
>. The increment and decrement operators also introduce side-effects,
Also, since these operators operate using blocking semantics, they are not
generally useful for synthesizable code (except in for loop indexes.)
If one is looking for a shorthand for loop construct, why not introduce a
foreach () operation.
"If I had a nickel for every time I've written "for (i = 0; i < N; i++)"
in C I'd be a millionaire."
- Mike Vanier
>2. IEEE 1364-2001 already considered and rejected the do-while construct.
> If SystemVerilog is going to claim to be based on the Verilog-2001
> standard, it should be fixed so that it actually is based on it.
Several of the testbench code examples for associative arrays and lists
use the do-while syntax for iteration. If we don't have a do-while
loop construct, then we should provide better support for iterating through
these containers.
These methods are based on STL, which is reference/pointer based. Why not support
a foreach generator method instead which can be used with a while () loop construct.
>1. The unique and priority keywords appear to be synthesis attributes.
> Verilog-2001 already added attributes, which can be used for such
> things. The checks for unique and priority behavior at run-time
> are potentially inefficient. And if someone wants them, that is
> what assertions are for.
These should also have simulation semantics (which they appear to do) but are
inconsistent. Consider:
Section 8.3, "A unique if ... A software tool should issue an error if it determines
that there is a potential overlap in the conditions."
2 paragraphs later, "If the case is qualified as priority or unique, the simulator
shall issue a warning message if an unexpected case value is found."
These (inconsistent) specifications are the same as an assertion. By default, assertions
report an error (with $error()) when they fail. If this functionality is kept,
the spec should say (consistently):
"A software tool shall call $error() if it determines that there is a potential
overlap in the conditions."
"If the case is qualified as priority or unique, the simulator shall call $error()
if an unexpected case value is found."
Warning are ignored. Here are cases where the user explicitly said, "This should not
happen." When they do that, they should be informed in a clear manner - you made an error.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Wed Dec 11 2002 - 08:42:04 PST