Subject: Logic Data Type Proposals - 20021209
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Dec 09 2002 - 17:50:23 PST
Hi, All -
The attached document proposes the following:
- allow logic to have multiple drivers (same with bit, real, struct
and int).
- do not permit last-assignment wins behavior outside of the current
scope.
- (assuming the above two conditions) make logic the default type for
SystemVerilog
- add a new type called ulogic (unresolved logic) that does the exact
same thing as logic but prohibits multiple drivers - OR - a new option:
`default_nettype unresolved (the second alternative means that we would not
need new keywords: ulogic, ubit, ureal, ustruct, uint).
- Define resolution tables for each of the new types.
- Add a new compiler directive: `default_resolution bit 0 (or 1)
- Possibly add user-defined default resolution capability for real,
struct and int, with permitted legal values
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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