Subject: SV 3.1 draft 1 LRM available
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Tue Dec 03 2002 - 13:55:41 PST
All,
Draft 1 of the SystemVerilog 3.1 is available for you to download and
print. This draft reflects the addition of the TestBench donation, as
specified by the SV-EC committee.
You can download the PDF document from:
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
All text that was added in this draft are highlighted as blue text, with
change bars in the margins. There is a lot--it roughly doubles the size of
the 3.0 LRM!
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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