Agenda And Attendance List -Second SystemVerilog Face to Face mee ting - December 4 - Mentor Graphics - San Jose


Subject: Agenda And Attendance List -Second SystemVerilog Face to Face mee ting - December 4 - Mentor Graphics - San Jose
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Nov 29 2002 - 08:35:36 PST


> Hello SystemVerilog Members,
> We will hold our second SystemVerilog meeting in San Jose on
> December 4th. Our host is Dennis Brophy. A list of confirmed attendees is
> appended at this email. A conference
        call be arranged but do not expect a good service (big room, many
people, etc.)

> Date: December 4th.
> Time: 9 AM Until 3:00 AM.
> Place: Mentor Graphics in San Jose.
         1001 Ridder Park Drive, San Jose
        Map:
http://maps.yahoo.com/py/maps.py?Pyt=Tmap&addr=1001+Ridder+Park+Drive&csz=sa
n+jose%2C+ca+95131&Get%A0Map=Get+Map

> Planned Agenda:
        (All Presenters : Please Send Me you presentation in advance -
PowerPoint
        Otherwise bring a Floppy).

9:00 - 9:15 Introduction Vassilios Gerousis
9:15 - 10:15 SV committee status (all four committees). Each chair has 15
minutes.
                SV Basic Johny Srouji / Karen Pieper
                SV Assertion Faisal Haque.
                SV C interface Swapnajit Mittra.
                SV Enhancement David Smith.
10:15 - 10:30 Break
10:30 - 12:00 Scheduling of event and semantics for SV 3.1 (Possibly Peter
Flake): A presentation of how Testbench, Assertion, SV 3.0 are connected
together in terms of events, synchronization and associated semantic.
12:00 - 12:30 Lunch
12:30 - 2:30 Technical Presentation (technical progress of each
committee).
> a- Assertion (SVA): Latest SVA LRM. (0.5 hour)
> b- Direct-C (SVC): Latest SVC LRM (0.5 hour)
> c- Changes expected or proposed by basic (0.5 hour).
> d- Enhancement and Testbench (SVT): Latest LRM and
> completed proposals.
2:30 - 2:45 Break
2:45 - 3:00 Patent Discussions
                 I will present my understanding of 0-in patent and ask
opinions on how to proceed. I am also in discussion with 0-in
in the hope that they cooperate with Accellera.
3:00 - 4:00 Cadence Analysis of SystemVerilog Standard (Jay Lawrenace).
4:00 - 4:30 Summary and Actions.

> SV Chairs meeting (4:30 to 5:30 PM) -- For the chairs only.
>
Attendees List = 30 Attendees.

David Smith
Stephen Boyd
Karen Pierper.
Johny Srouji
Faisal Haque
Stephen Meier
Swapnajit Mittra
Ghassan Khoury
Peter Flake
Jayant Nagda
Jay Lawrence
Harry Foster
Erich Marschner
Connie ODell
Stuart Sutherland
        Clifford E. Cummings
        Joe Daniel
        Tejbal Singh
        Kevin Cameron
        Neil Korpusik
        Bassam Tabbara
        Mehdi Mohtashemi
        Alec Stanculescu
        Stuart Swan
        Prakash Narain
        Zain Navabi
        Dave Rich
        Richard Ho
        Dennis Brophy
        Vassilios Gerousis

> --------------------------------------------------------------------------
> ----------------------------------------------------
> Dr. Vassilios Gerousis
> Chief Scientist
> Infineon Technologies
> DAT CS, MchB
> D-81541 Munich
> Germany
> BalanSt. 73
> Telephone: +49-89-234-21342
> Fax: +49-89-234-23650
> email: Vassilios.Gerousis@infineon.com
> Site Map:
> http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
> --------------------------------------------------------------------------
> --------------------------------------------------------
>
>



This archive was generated by hypermail 2b28 : Fri Nov 29 2002 - 08:37:39 PST