Subject: Re: Interface Notes - 20021127
From: Kevin Cameron (sv-xx@grfx.com)
Date: Thu Nov 28 2002 - 11:41:09 PST
> From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
>
> Hi, All -
>
> Some thoughts about interfaces for your consideration.
>
> Regards - Cliff
I think the problem is that we have too many ways of doing the
same thing. If all an interface is supposed to do is bundle wires
together then we could do that with "structs" and "unions" (as
per VHDL) and with (.*) - though personnally I would rather not
have (.*).
What interfaces really are (IMO) is a step towards object-oriented
Verilog. Just as C evolved into C++ which supports object/method
methodology with classes, overloading and virtual functions and the
concept of public and private data, SV allows functionality to be
buried in an interface. The problem is that it is just a step in
that direction, there are a bunch of things not quite right:
1. It shouldn't be a seperate object it should just be an
extension of module so that it can have internal hierarchy.
2. It should support inheritance like C++ classes so that you
can do things like defining an abstract interface and inherit
its functionality (assertions etc.) into different
implementations.
3. It needs to support back-annotation for verifying gate-level
implementations.
Having said that, I do still think "interfaces" are a step in the
right direction.
Kev.
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