Subject: Re: Logic Data Types need fixing
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Nov 26 2002 - 23:54:17 PST
Nice try Cliff!!
Let me try to separate your proposal into some manageable chunks.
1. interfaces and logic are completely independent of each other. How do
you feel they are related?
2. reg is obsoleted by logic. We could have just extended the
functionality of reg to behave like other SV variables and still have
been 100% backward compatible. However people (like yourself) thought
this was too dramatic a change; people would get lost if they didn't get
their dosage of "illegal left-hand-side assignment" error messages. So
logic was created to distance itself from the legacy "reg" behavior.
Moving forward, there is no longer a reason to teach people about reg.
Perhaps you should propose that we remove logic and eliminate the
original restrictions on reg.
3. The current spec does not rule out the possibility of removing the
single driver restriction at a later time. This will also require
strength resolution in logic,
4. I think your #2 proposal is good even without allowing multiple
drivers. Over 99% of all signals do not have multiple drivers and do not
require strength resolution. This would force people to declare nets
with multiple drivers, which I think is a good thing. Again, I don't see
anything we are doing now that would rule this out later.
Dave
Clifford E. Cummings wrote:
> Hi, All -
>
> Attached is an analysis of, and a proposal to fix the SystemVerilog
> 3.0 "logic" data type. I'm not sure which committee should take this
> up. It is both a fix and an enhancement.
>
> Regards - Cliff
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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