Subject: Re: Clarification for SV-BC18h and 18i
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Nov 25 2002 - 23:12:38 PST
> 5.6 Nets, regs, and Other Variables
> Replace with:
>
> Verilog 2001 also states that reg variables can only be written by one
> or more procedural statements, including procedural continuous
> assignments. The last write determines the value. The force statement
> overrides the procedural assign statement which in turn overrides the
> normal assignments. A reg variable cannot be written through a port, it
> must go through an implicit continuous assignment
The last half-sentence is not clear.
What does "it must go through an implicit continuous assignment" refer to,
and what does it mean?
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478"The devil is in the details."
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