Subject: Re: SystemVerilog 3.0 Is An Accellera Standard
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Nov 18 2002 - 09:34:48 PST
> From: Vassilios.Gerousis@Infineon.Com
>
> Dear SV-BC members,
> I want to clarify that SystemVerilog 3.0 is an Accellera Standard.
> We have offered to help clarify or enhance SystemVerilog. As language
> becomes a standard, users and EDA vendors must look at this as a stable
> standard ready for implementation. We also need to have a stable base to
> help in the development of additional components of SystemVerilog 3.1. We
> have provided an opportunity to correct mistakes or problems that were
> encountered during implementation. Harry Foster has implemented one of the
> assertion and found a mistake and this is being corrected, as an example.
> Intel is providing good feedback on the BNF.
> As we put the different components we may have to adjust certain
> things, but that will be kept at minimum. So I urge you that examine your
> work as clarification and enhancements to the existing capabilities. If the
> interface require additional improvement, then you need to build a proposal
> to do so.
>
> Best Regards
>
> Vassilios
It became apparent at Friday's meeting that there are some major issues with
some language features (e.g. passing variables through ports) with respect
to back-annotation (SDF). Can the BC remove features of the language that
do not work in a front-to-back design flow?
Kev.
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