Subject: Second SystemVerilog Face to Face meeting - December 4 - Mentor G raphics - San Jose
From: Vassilios.Gerousis@Infineon.Com
Date: Thu Nov 07 2002 - 21:56:57 PST
Hello SystemVerilog Members,
We will hold our second SystemVerilog meeting in San Jose. Our host
will be Dennis
Brophy at Mentor Grphics. This is a face to face meeting and your presence
is encouraged. We will try to provide a teleconference, but the phone is not
idea for large crowd in a big conference.
Date: December 4th.
Time: 9 AM Until 3:00 AM.
Place: Mentor Graphics in San Jose.
Planned Agenda:
1- SV committee status (all four committees).
2- Scheduling of event and semantics for SV 3.1 (Possibly Peter
Flake): A presentation of how Testbench, Assertion, SV 3.0 are connected
together in terms of events, synchronization and associated semantics.
3- Technical Presentation:
a- Assertion (SVA): Latest SVA LRM.
b- Direct-C (SVC): Latest SVC LRM
c- Changes expected or proposed by basic: Proposals
d- Enhancement beyond Testbench (SVT): Latest LRM and
completed proposals.
4- Patent Discussions: I will present my understanding of 0-in
patent and ask opinions on how to proceed. I am also in discussion with 0-in
in the hope that they cooperate with Accellera.
5- SV analysis.
6- SV Chairs meeting (3:00 to 5:00 PM) -- For the chairs only.
You are required to RSVP in order to hold a place for you. Seating
is limited.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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