Subject: Donations By Cadence
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Sep 02 2002 - 21:11:49 PDT
On June 5th (May/April) Cadence announced that they would like to donate
complimentary
technology to SystemVerilog 3.1 (Assertions, Datapath and API_. When I ask,
I keep told,
the lawyers have issues with the technology assignment letter from
Accellera. Cadence
did not share the issues or the changes they would like to see. I asked them
but they do
not tell. This is extremely surprising and I cannot understand the
situation.
Please note that IBM, Intel, Synopsys and many other signed similar document
in a maximum
of one month. Each company required changes in the letter. IBM, Intel and
Synopsys reported
to me the changes and we discussed with Accellera and made changes, all in
one month.
The technical chairs of SystemVerilog have set a date of September to submit
all
donations. We must proceed with milestones that we set up. Our main goal is
to get
SystemVerilog 3.1 to IEEE committee for standardization. We cannot wait any
more.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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