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Verilog Analog/Mixed-Signal (AMS) Working Group

Charter

To develop, update and promote analog and mixed-signal extensions to the Verilog (IEEE-1364) language.

Chair: Scott Little, Intel
Vice-Chair: Martin O'Leary, Qualcomm

Scope

The working group is currently working on alignment of Verilog-AMS with the SystemVerilog work of the IEEE 1800, or inclusion of AMS capabilities in a new "SystemVerilog-AMS" standard. In addition, work is underway to focus on new features and enhancements requested by the community to improve mixed-signal design and verification, as well as to extend SystemVerilog Assertions to Analog and Mixed-Signal designs through the subcommittees.

Background

Accellera approved the Verilog-AMS LRM, version 2.3.1 in June 2009. This version supersedes previous versions of the Verilog-AMS LRM.

Verilog-AMS benefits users by allowing them to describe and simulate analog and mixed-signal designs using a top-level design methodology as well as the traditional bottom-up approaches. The Verilog-AMS standard supports analog and mixed-signal designs at three levels: transistor/gate, transistor/gate-RTL/behavioral, and mixed transistor/gate-RTL/behavioral circuit levels. Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical, and thermal are important.

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