SystemC Verification Working Group (VWG)
The Verification Working Group (VWG) is responsible for defining verification extensions to the SystemC language standard, as well as enriching the SystemC reference implementation by offering an add-on SystemC Verification (SCV) library to ease the deployment of a verification methodology based on SystemC.
Chair: Mr. Jerome Cornet, STMicroelectronics
Vice-Chair: Dr. Axel Braun, Universität Tüebingen
SystemC is one of the key languages used for verification activities. Beyond SystemC’s built-in capabilities, verification extensions to its API are needed to avoid reinventing the same mechanism all over again and to provide a stable framework onto which tools suppliers can build added value. As SystemC is a system-level specification methodology, this includes the application of verification approaches on abstract levels, besides hardware potentially also covering RTOS and software.
The current SystemC Verification (SCV) library (version 1.0p2) already provides a common set of APIs that are used as a basis to verification activities with SystemC (generation of values under constraints, transaction recording, etc.). These APIs are implemented in all major SystemC simulators available on the market.
As verification needs in SystemC evolve and communication with other languages is more and more frequent, additions to the existing set of APIs are required. For example, these additions will also focus on coverage analysis and temporal assertion checking mechanisms and their interfacing and/or integration into the SystemC language. Standardizing these additions is crucial to allow seamless migration of models from the environment of one tool supplier to another. This integration process also includes the analysis and evaluation of interfaces to existing ASI verification approaches like UVM and their seamless integration into a SystemC-based verification process.
SCV 1.0p2 is compatible with SystemC 2.2 as well as the earlier SystemC V2.1v1.
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