Open Verification Library (OVL) Working Group
To define and deliver standard OVL LRM and libraries of assertion checkers to be used by design, integration and verification engineers to check for good/bad behavior in simulation, emulation and formal verification – provided in Verilog, System Verilog, VHDL, PSL, and SystemC.
Chair: Kenneth Larsen, Mentor Graphics
The OVL library of assertion checkers is intended to be used by design, integration, and verification engineers to check for good/bad behavior in simulation, emulation, and formal verification.
The Open Verification Library (OVL) subcommittee is responsible for the definition and development of the standard OVL language reference manual and assertion-checker libraries.
OVL Version 2.8, released in December 2013, is the latest OVL release implemented in Verilog, VHDL, System Verilog and PSL (Verilog flavor).
Join this Subcommittee
If you are an employee of a member company and would like to join this subcommittee, click here (requires login) and click Join Group.
- Errata and feedback: To report or see current errata of the standard OVL library, click here (Mantis reporter login required; select the standard OVL errata page). If you would like to report errata but are not a Mantis reporter, please send a message to the OVL chairs.