Intellectual Property (IP) Tagging Technical Subcommittee
To tag soft IP to enable date-driven tracking of soft IP usage.
This group develops a standard to support the tracking of soft design IP through the development process such that it can be readily identified in a final GDSII database. This facilitates a data-driven method to track IP “where used” for applications such as ownership, royalty calculations and recognition; implemented version identification for applicable bug fixes and errata; and others. The work will align with the VSIA-developed Virtual Component Identification Physical Tagging Standard, (Hard IP Tagging Standard) and will evaluate and update the Virtual Component Identification Soft IP Tagging Standard to reflect this new usage paradigm.
IP tagging provides a way to track both hard IP and non-hardened or soft IP information throughout the design and development process. The design process can include editing, synthesis, timing, placement, wiring, and other steps leading to GDSII generation. Semiconductor foundries, providers of IP blocks, and manufacturers of design tools can use the methods described in this standard to track identification information throughout each level of the development process. At each level, tracking information is obtained from the previous level and is transported to the next level using the appropriate output format.
Note that this standard specifically addresses the passing of information throughout the design process. It does not consider the protection of the intellectual property (IP). The passing methods described in this standard are not secure, so they are potentially susceptible to tampering. These methods are intended only to facilitate the passing, use, and sharing of information among honest IP users and IP providers, helping to ensure the quality of the final design. Nevertheless, the mere existence of these methods does afford a low-level form of security.
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