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systemc-forum - RE: [systemc-forum] Modeling tri-state signal
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- From: "Somervill, Kevin M. (LARC-D203)" <kevin.m.somervill@xxxxxxxx>
- Date: Tue, 20 Mar 2012 12:13:22 -0500
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I replied directly to David, apologies.
PEBKAC. In setting the hi-z state for my vector, I used .write(“Z”) as opposed to .write(“ZZZZZZZZ”). Is there a way to an entire array to a value similar to (others => ‘Z’) in VHDL?
From: david.black@xxxxxxxxxx [mailto:david.black@xxxxxxxxxx]
Sent: Monday, March 19, 2012 10:43 AM
To: Somervill, Kevin M. (LARC-D203)
Subject: Re: [systemc-forum] Modeling tri-state signal
sc_signal_rv is the correct approach. You probably need to post your code here if you want help.
David C Black, Senior Consulting Engineer
Doulos Inc http://www.Doulos.com
Voice: 512.850.4322 Skype: dcblack FAX: 888.467.4609
Doulos - Developing Design Know-how
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-----<systemc-forum@xxxxxxxxxxxxxxxxxxx> wrote: -----
To: "systemc-forum@xxxxxxxxxxxxxxxxxxx" <systemc-forum@xxxxxxxxxxxxxxxxxxx>
From: "Somervill, Kevin M. (LARC-D203)"
Date: 03/19/2012 07:22AM
Subject: [systemc-forum] Modeling tri-state signal
I’m trying to model bidirectional I/O (at a low level) and I get the multiple drivers error or what I believe is incorrect resolution on ‘Z’. I’ve been googling for about a week and have not found anything that shows me how to model tri-state signal. In the spec, it states that I should use sc_signal_rv, but I don’t get the expected output. If I drive a ‘Z’ at one place and a ‘1’, I get ‘X’. If I drive a ‘Z’ from one driver, but a ‘0’ from the other, I get a ‘0’. I expect that there’s an obvious fix for this issue, but I’ve not been able to find it. Any suggestions?