KMLM List

["Bradley, Mike" <mike_bradley@xxxxxxxxxx>]

Hi,

I don't think you can have very good "AT" performance without taking
burst transfers into account.  Indeed most CPU data transfers and
instruction read will be cache line accesses, which are bursts.

Would not TLM 2.0 be able to timing-model this?  If not, and you have to
go down to RTL and back, seems like a kludge. 

-Mike

-----Original Message-----
From: Bernard Deadman [mailto:bdeadman@xxxxxxxxxx] ;
Sent: Thursday, October 21, 2010 10:45 AM
To: A, Nizamudheen
Cc: Bradley, Mike; systemc-forum@xxxxxxxxxxxxxxxxx
Subject: Re: [systemc-forum] TLM2.0 timing diagram w/ for multiple burst
transaction


Hi Nizam,

TLM basically models memory reads / writes and most of the TLM models 
achieve a compromise between performance and accuracy without 
considering how block transfers are broken down into word reads & writes

on a bus, so there's no standardization for this level of precision. As 
an example we deliver transactors that interface / convert TLM to RTL 
buses like AXI & OCP that support burst mode transfers. The transactors 
are fully protocol compliant at the cycle-level but the TLM still 
operates with a byte array & length payload.

The disadvantage of modeling the individual transfers in TLM is, of 
course, performance. Taken to extremes the TLM models are going to 
replication what the RTL does to get the accuracy at the word transfer 
level (almost cycle-accurate in most cases) but then you lose the 
performance advantage from using TLM so why not stick with the RTL and 
avoid the cost of creating the second set of models?

Perhaps we can help you better if you can explain your goals in modeling

at this level of precision in a TLM environment?

Regards

Bernard



A, Nizamudheen wrote:
>
> Hi Mike,
>
> Thanks for your response.
>
> I was trying to create an extension to the base-protocol and I 
> couldn't find any example or statement in LRM regarding multi-burst 
> transaction.
>
> Regards,
>
> Nizam
>
>
------------------------------------------------------------------------
>
> *From:* systemc-forum@xxxxxxxxxxxxxxxxx 
> [mailto:systemc-forum@xxxxxxxxxxxxxxxxx] *On Behalf Of *Bradley, Mike
> *Sent:* Thursday, October 21, 2010 7:26 PM
> *To:* systemc-forum@xxxxxxxxxxxxxxxxx
> *Subject:* RE: [systemc-forum] TLM2.0 timing diagram w/ for multiple 
> burst transaction
>
> Hi Nizam,
>
> I Looked around but could not find one. Best I could find is in the 
> TLM2.0 LRM. There are commercial tools that implement TLM2.0 burst 
> transactions for you (only one I know of is Vista from Mentor, but I'm

> sure there are others). Have you looked at commercial solutions, or 
> just wanting to create your own?
>
> -Mike
>
> *From:* systemc-forum@xxxxxxxxxxxxxxxxx 
> [mailto:systemc-forum@xxxxxxxxxxxxxxxxx] *On Behalf Of *A, Nizamudheen
> *Sent:* Tuesday, October 19, 2010 7:06 AM
> *To:* systemc-forum@xxxxxxxxxxxxxxxxx
> *Subject:* [systemc-forum] TLM2.0 timing diagram w/ for multiple burst

> transaction
>
> Hi,
>
> Can some-one point me to a TLM2.0 transaction diagram for a 
> multi-burst read/write transaction?
>
> Regards,
>
> Nizam
>