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  • To: systemc-forum@xxxxxxxxxxxxxxxxx
  • From: Kevin Im <jylim3@xxxxxxxxxxx>
  • Date: Sun, 10 Jan 2010 16:03:10 +0900
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Dear all

I have designed some module with systemc.

But, i have encountered strange error in my code.

Here is codes.

cache.h
        .....
        SC_METHOD( cache_process );
        sensitive << clk;
        sensitive << RSTb;
    ...

        sc_signal< sc_uint<1> > CACHE_HIT  ;
        sc_signal< sc_uint<1> > CACHE_MISS ;
    ....

cache.cpp
        .....
        cache_process()
        {
                .......
        // Cache Hit
        sc_uint<1> CACHE_HIT_int ;
        sc_uint<1> CACHE_MISS_int;
        
CACHE_HIT_int = ( ( ( WAY_0_HIT == 1 || WAY_1_HIT == 1 || WAY_2_HIT == 1 || WAY_3_HIT == 1 ) && ( ENABLE_CACHE.read() == 1 ) && ( CACHE_ENABLE_AREA_int == 1) ) )? 1 : 0 ;
        CACHE_HIT.write( CACHE_HIT_int ) ;
        
        
        if (CACHE_HIT_int == 0 )
                CACHE_MISS_int =  1;
        else
                CACHE_MISS_int =  0 ;
        
        CACHE_MISS.write( CACHE_MISS_int  ) ;
        ......
        
     }
        .....

As see in codes, there are same sequence code.

        ..
        CACHE_HIT.write( CACHE_HIT_int ) ;
        ...
        CACHE_MISS.write( CACHE_MISS_int  ) ;
        ....
        
Upper code did not generate any error, But, below code which write to CACHE_MISS is generate "bus error".
between two codes are not much difference except CACHE_MISS write value is generate from CACHE_HIT_int signal.

Any Reason to this situation ?
Is there anything i should  do other than that ?

Thanks and regards.
Kevin Im

 

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