Skip Nav
Home » Forums » SystemC Forum

Icon - KMLM List KMLM List

View email archives for the history of this mailing list.

List Home All Archives Dates Threads Authors Subjects
systemc-forum - Problem in Assignment for single bit of SC_Logic_Vector Message Thread: Previous | Next
  • To: "systemc-forum@xxxxxxxxxxxxxxxxx" <systemc-forum@xxxxxxxxxxxxxxxxx>
  • From: Jyotshna_Sharma <Jyotshna_Sharma@xxxxxxxxxx>
  • Date: Mon, 3 Aug 2009 17:37:25 +0530
Send Email to systemc-forum@lists.systemc.org:
Send new message
Reply to this message
Hi,
I am trying to assign value to the bits of an sc_lv one by one on per clock 
basis.
The part of code is as:
#define data_width 4
SC_MODULE(shifter)
{
            sc_in<bool> clock;
            sc_in<sc_logic> data_in;
            sc_out<sc_lv<data_width>> data_out;
int i;


....
for(i=0;i<data_width;i++)
{
            data_out[i]=data_in;   //AT THIS LINE I AM GETTING THE ERROR
            if(i<=data_width)
            {
                        data_ended=1;
            }
}
...
};
But getting an error like..
error C2440: '=' : cannot convert from 'sc_core::sc_in<sc_dt::sc_logic>' to 
'sc_core::sc_signal_inout_if<T> *'
        with
        [
            T=sc_dt::sc_lv<4>
        ]

Exactly where the problem lies?





________________________________
DISCLAIMER:
This email (including any attachments) is intended for the sole use of the 
intended recipient/s and may contain material that is CONFIDENTIAL AND PRIVATE 
COMPANY INFORMATION. Any review or reliance by others or copying or 
distribution or forwarding of any or all of the contents in this message is 
STRICTLY PROHIBITED. If you are not the intended recipient, please contact the 
sender by email and delete all copies; your cooperation in this regard is 
appreciated.

By Date: Previous | Next Current Thread By Thread: Previous | Next