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systemc-forum - Problem in Assignment for single bit of SC_Logic_Vector
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- To: "systemc-forum@xxxxxxxxxxxxxxxxx" <systemc-forum@xxxxxxxxxxxxxxxxx>
- From: Jyotshna_Sharma <Jyotshna_Sharma@xxxxxxxxxx>
- Date: Mon, 3 Aug 2009 17:37:25 +0530
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Hi,
I am trying to assign value to the bits of an sc_lv one by one on per clock
basis.
The part of code is as:
#define data_width 4
SC_MODULE(shifter)
{
sc_in<bool> clock;
sc_in<sc_logic> data_in;
sc_out<sc_lv<data_width>> data_out;
int i;
....
for(i=0;i<data_width;i++)
{
data_out[i]=data_in; //AT THIS LINE I AM GETTING THE ERROR
if(i<=data_width)
{
data_ended=1;
}
}
...
};
But getting an error like..
error C2440: '=' : cannot convert from 'sc_core::sc_in<sc_dt::sc_logic>' to
'sc_core::sc_signal_inout_if<T> *'
with
[
T=sc_dt::sc_lv<4>
]
Exactly where the problem lies?
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- Problem in Assignment for single bit of SC_Lo, Jyotshna_Sharma (you are here)
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