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systemc-forum - RE: [Systemc-forum] Multiple verilog blocks with SystemC
- To: "James Watt" <jwatt@xxxxxxx>, "David C Black" <dcblack@xxxxxxxx>
- From: "Stuart Swan" <stuart@xxxxxxxxxxx>
- Date: Tue, 31 May 2005 11:12:28 -0700
- Cc: <Systemc-forum@xxxxxxxxxxx>
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sc_start() also causes SystemC elaboration to occur if it has
not already occurred. It is quite possible that there is a bug in your
design that causes the segfault during elaboration, and that is what
you are seeing. You may want to inspect the module ctors of recently
added modules, run your design using purify, test your design on a
compiler/platform, etc., to try to identify
[mailto:systemc-forum-admin@xxxxxxxxxxx] On Behalf Of James Watt
Sent: Tuesday, May 31, 2005 10:18 AM
To: David C Black; James Watt
Subject: RE: [Systemc-forum] Multiple verilog blocks with
> -----Original Message-----
> From: David C Black [mailto:dcblack@xxxxxxxx]
> Sent: Tuesday, May 31, 2005 12:56 PM
> To: James Watt
> Cc: Systemc-forum@xxxxxxxxxxx
> Subject: Re: [Systemc-forum] Multiple verilog blocks with
> > Any ideas what the problem might be? What does sc_start()
> > might cause a segfault?
> sc_start() begins the simulation. It starts the kernel, which
> schedules processes (SC_METHOD's & SC_THREAD's) to run.
> Does it matter where in the hierarchy your models are?
Yes. We have SC code at the top level that drives data into the
> Whose simulator are you using for the Verilog part?
Cadence, but I have similar problems when using a
hardware/software cosimulator (time won't start because of segfault).
When using the hardware/software cosim I get the entire design in RTL
and just use the SystemC top level to drive the data in and check the
data as it comes out.
> David C Black
> Your innovative SystemC design professional
> Voice/FAX: +1888.467.4609