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systemc-forum - Re: [Systemc-forum] Multiple verilog blocks with SystemC
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- To: James Watt <jwatt@xxxxxxx>
- From: David C Black <dcblack@xxxxxxxx>
- Date: Tue, 31 May 2005 11:56:10 -0500
- Cc: Systemc-forum@xxxxxxxxxxx
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Any ideas what the problem might be? What does sc_start() do that
might cause a segfault?
sc_start() begins the simulation. It starts the kernel, which
schedules processes (SC_METHOD's & SC_THREAD's) to run.
Does it matter where in the hierarchy your models are?
Whose simulator are you using for the Verilog part?
David C Black
Your innovative SystemC design professional
http://www.ESLX.com
Voice/FAX: +1888.467.4609
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