> -----Original Message-----
> From: Bill Dittenhofer [mailto:bill_dittenhofer@xxxxxxxxxxx]
> Sent: 08 September 2004 19:19
> To: systemc
> Subject: [Systemc-forum] Casting 2 level types to 4 level types
> This is ok inside the model, but causes problems when comparing
> an RTL signal with the SystemC signal in a SystemC module.
> This is due
> to the RTL generating X's, Z's of various strengths. When
> converting this to a 2 value SystemC signal, the X's and Z's
> get "resolved", usually to a '0'. This causes X's, Z's from
> the RTL to get missed by the comparator.
> It would be desirable to cast the 2 value signal from inside the
> model to a 4 value signal. The model doesnt produce X's,
> Z's, so nothing would be lost. The RTL value could be
> transported using a 4 valued signal, and X's, Z's would be detected.
> Is it possible to cast the 2 valued (model) signal to
> a 4 valued signal?
I'm not sure I quite understand what you're doing. If I understand
correctly, you have an RTL Verilog or VHDL model instanced inside a
SystemC verification environment. Signals from the Verilog module may
contain X and Z.
Inside the SystemC model, I guess they appear as sc_signal<sc_logic> or
sc_signal<sc_lv<> >, and may still contain 'X' and 'Z'.
You're then comparing them with reference values from a SystemC model which
are either sc_signal<sc_bv<> > or sc_signal<bool>
if (dutsig == refsig)
and operator== defined to compare sc_logic and bool is losing the 'X' and 'Z'
I don't think you can cast, but you should be able to use assignment. The
simplest thing is to use a temporary variable. For instance
sc_lv<8> ref_vector_temp = refvector; // convert from sc_bv to sc_lv by
sc_logic ref_bit_temp = ref_bit; // convert from bool to sc_logic by
if (dut_vector == ref_vector_temp) // now comparing two sc_lvs
if (dut_bit == ref_bit_temp) // now comparing to sc_logic
You'd then just need additional variable assignments which should
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