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systemc-forum - RE: [Systemc-forum] calling verlog system task in SystemC Message Thread: Previous | Next
  • To: "Chun Lin Zhang" <chun_lin_zhang@xxxxxxxxxxx>, <systemc-forum@xxxxxxxxxxxxxxxxxxx>
  • From: "Stuart Swan" <stuart@xxxxxxxxxxx>
  • Date: Mon, 14 Apr 2003 11:03:48 -0700
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Chun Lin-
This isn't supported yet in NC-SystemC / Incisive. A simple way to 
achieve this is to have a verilog module with an always block that is
sensitive to a signal triggered from the systemc side. When you want
to call the verilog task, assign the task arguments as signals on the
side and trigger the triggering signal. Then on the Verilog side within
the always
block, read the task arguments from the signals and call the task.

        -----Original Message-----
        From: Chun Lin Zhang [mailto:chun_lin_zhang@xxxxxxxxxxx] 
        Sent: Thursday, April 10, 2003 10:19 PM
        To: systemc-forum@xxxxxxxxxxxxxxxxxxx
        Subject: [Systemc-forum] calling verlog system task in SystemC
        Hi, everybody
        Anybody know how to call a verilog system task in SystemC when I
do the co-sim of with NC-SystemC/NC-Verilog?

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