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systemc-forum - [Systemc-forum] Interfacing HDL (VHDL/VerilogHDL) to SystemC Model
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- To: <systemc-forum@xxxxxxxxxxx>
- From: "goodkook" <goodkook@xxxxxxxxxxxxxxxx>
- Date: Sat, 6 Apr 2002 20:20:30 +0900
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This is example of co-simulation : SystemC model & HDL including VHDL and
VerilogHDL.
It's similar to my previous posting, "Interfacing VHDL & SystemC Model"
In this example, SystemC model is interfaced to HDL, not only VHDL, but also
VerilogHDL.
For HDL interface, MTI FLI and PLI is used.
Download:
http://www.anslab.co.kr/download/SystemC/SC_Win32_HDL.zip
The example includes,
1. SystemC model and testbench
2. SystemC & Win32 GUI interface
3. VHDL-FLI, SystemC and Win32 GUI interface
4. VerilogHDL-PLI, SystemC and Win32 GUI interface
Regards,
Kook
----------------------------------------------------------------
Kook, ilho, Ph.D.
President / AnsLab Co.,Ltd. / http://www.anslab.co.kr
E-mail: goodkook@xxxxxxxxxxxxxxxx
Phone: +82-2-571-7670
Fax: +82-2-573-5801
Cell: +82-11-9401-4791
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