hi,
can we generate the clock like :
sc_clocl clk("clk",9.9,.5,0,true);
even i can't use the odd number like;
sc_clocl clk("clk",11,.5,0,true);
it is compiling and running But i couldn't see the wave form in vcs tool,
please anybody make clear it.
Thanks
saravanan
-----Original Message-----
From: Martin Janssen [mailto:Martin.Janssen@xxxxxxxxxxxx]
Sent: Thursday, April 04, 2002 7:54 PM
To: David Long
Cc: Asif CN; systemc-forum@xxxxxxxxxxxxxxxxxxx
Subject: Re: [Systemc-forum] clock
Hi David, Asif,
With SystemC 2.0.1 (planned for mid April) sc_signal<sc_logic> and
the associated ports will know positive and negative edges, so you
can make processes sensitive to the positive edge or negative edge
of such a signal. Just like in VHDL and Verilog, a positive edge on
a sc_logic signal is a transition from non-one to one, whereas a
negative edge is a transition from non-zero to zero.
Martin
-oo-
David Long wrote:
> Asif,
>
> There is no fundamental reason why you cannot use a signal of any type
> as a "clock" i.e. a periodic signal used to trigger processes.
>
> I suspect you are asking how to generate such a signal from an sc_clock
> channel. You can do this inside a process that is sensitive to the
> clock.
>
> e.g
>
> SC_MODULE(clock_gen) {
> //ports
> sc_out<sc_logic> clk;
>
> //internal clock
> sc_clock i_clk;
>
> //processes
> void do_proc() {
> if i_clk.read() clk.write(sc_logic_1);
> else clk.write(sc_logic_0); }
>
> SC_CTOR(clock_gen):i_clk("ICLK", 10, SC_NS)
> {
> SC_METHOD(do_proc);
> sensitive << i_clk;
> }
> };
>
> Your next problem is how to use this clock to trigger other modules.
> Unfortunately you cannot say
>
> sensitive_pos << clk;
>
> since this only works with bool signal ports so the processes must be
> triggered by any clock transition.
>
> If you look at the sc_signal<sc_logic> class (in sc_signal.h> you may
> notice functions to detect positive and negative edges. Unfortunately,
> these are not part of the interface class used by sc_in/sc_out so you
> cannot use them on your clock port.
>
> Here is a possible solution:
>
> SC_MODULE(test) {
> sc_in<sc_logic> clk;
>
> void do_proc1() {
> while (true)
> {
> cout << "Positive clock at " << sc_time_stamp() << endl;
> do wait(); while ( Clock.read() != sc_logic_1);
> }
> }
>
> void do_proc2()
> {
> if (Clock.read()== '0' ) {
> cout << "Negative clock edge at " << sc_time_stamp() << endl;
> }
>
> SC_CTOR(test)
> {
> SC_THREAD(do_proc1);
> sensitive << clk;
> SC_METHOD(do_proc2);
> sensitive << clk;
> }
> };
>
> As you can see, it is much easier to use sc_clk and associated ports
> unless you have a good reason not to. If you have a common requirement
> to use your own clock types, I suggest you create your own clock channel
> - look at how the sc_clock hierarchical channel and its interfaces are
> written.
>
> Dave
>
>
> In message <20020404115649.14490.qmail@xxxxxxxxxxxxxxxxxxxxxxx>, Asif CN
> <asifcn@xxxxxxxxx> writes
>
>> hi all,
>>
>> can we declare "clock" as <sc_logic> data type???
>>
>> ie, sc_in<sc_logic> clk;
>>
>> and then how we will generate a clock and port map to the
>> <sc_logic> clock in main module???
>>
>> please comment/advice on this.....
>>
>> thanks a lot
>>
>> Asif
>>
>>
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>>
>
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