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systemc-forum - Re: [Systemc-forum] clock Message Thread: Previous | Next
  • To: David Long <david.long@xxxxxxxxxx>
  • From: Martin Janssen <Martin.Janssen@xxxxxxxxxxxx>
  • Date: Thu, 04 Apr 2002 16:23:31 +0200
  • Cc: Asif CN <asifcn@xxxxxxxxx>, systemc-forum@xxxxxxxxxxxxxxxxxxx
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Hi David, Asif,

With SystemC 2.0.1 (planned for mid April) sc_signal<sc_logic> and
the associated ports will know positive and negative edges, so you
can make processes sensitive to the positive edge or negative edge
of such a signal. Just like in VHDL and Verilog, a positive edge on
a sc_logic signal is a transition from non-one to one, whereas a
negative edge is a transition from non-zero to zero.


David Long wrote:


There is no fundamental reason why you cannot use a signal of any type
as a "clock" i.e. a periodic signal used to trigger processes.

I suspect you are asking how to generate such a signal from an sc_clock
channel. You can do this inside a process that is sensitive to the


SC_MODULE(clock_gen) {
  sc_out<sc_logic> clk;

  //internal clock
  sc_clock i_clk;

  void do_proc() {
    if clk.write(sc_logic_1);
    else clk.write(sc_logic_0); }

  SC_CTOR(clock_gen):i_clk("ICLK", 10, SC_NS)
    sensitive << i_clk;

Your next problem is how to use this clock to trigger other modules.
Unfortunately you cannot say

sensitive_pos << clk;

since this only works with bool signal ports so the processes must be
triggered by any clock transition.

If you look at the sc_signal<sc_logic> class (in sc_signal.h> you may
notice functions to detect positive and negative edges. Unfortunately,
these are not part of the interface class used by sc_in/sc_out so you
cannot use them on your clock port.

Here is a possible solution:

SC_MODULE(test) {
  sc_in<sc_logic> clk;

  void do_proc1() {
    while (true)
      cout << "Positive clock at " << sc_time_stamp() << endl;
      do wait(); while ( != sc_logic_1);

  void do_proc2()
    if ( '0' ) {
      cout << "Negative clock edge at " << sc_time_stamp() << endl;

    sensitive << clk;
    sensitive << clk;

As you can see, it is much easier to use sc_clk and associated ports
unless you have a good reason not to. If you have a common requirement
to use your own clock types, I suggest you create your own clock channel
- look at how the sc_clock hierarchical channel and its interfaces are


In message <20020404115649.14490.qmail@xxxxxxxxxxxxxxxxxxxxxxx>, Asif CN <asifcn@xxxxxxxxx> writes

  hi all,

  can we declare "clock" as <sc_logic> data type???

  ie,       sc_in<sc_logic> clk;

and then how we will generate a clock and port map to the <sc_logic> clock in main module???

  please comment/advice on this.....

  thanks a lot


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