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systemc-forum - Re: [systemc-forum] HELP! " inverter (port not bound" error) Message Thread: Previous | Next
  • To: Salvatore Galfano <galfanosalvatore@xxxxxxxxx>
  • From: alan.fitch@xxxxxxxxxx
  • Date: Tue, 21 Feb 2012 10:30:49 +0000
  • Cc: systemc-forum@xxxxxxxxxxxxxxxxxxx, systemc-forum@xxxxxxxxxxxxxxxxx
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Oops,
  well-spotted again! I didn't even notice it was an SC_THREAD, not an SC_METHOD. Doh!

Alan

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From: Salvatore Galfano <galfanosalvatore@xxxxxxxxx>
To: systemc-forum@xxxxxxxxxxxxxxxxx
Date: 21/02/2012 10:24
Subject: Re: [systemc-forum] HELP! " inverter (port not bound" error)
Sent by: <systemc-forum@xxxxxxxxxxxxxxxxxxx>





Hi,

excuse me, what Alan said is of course correct.. But I guess the error
is in the fact that invert(void) was "declared" as a SC_THREAD.
SC_THREADs are executed only once (differently from SC_METHOD). So, in
order to make it work as you wish (or as I suppose you wish), you should
either put a while(true){ ... } wrap to your code inside invert(void),
or declare that function as a SC_METHOD (which executes many times). In
the first case you should change the code as follow:

void inverter::invert(void) {
                while(true){ //Added
                                 bool temp = ! A.read();
                                 Invert_A.write(temp);
                                 std::cout << "Time:" << sc_time_stamp()<< endl <<" inverter_Input : " << A << endl << " inverter_Output : " << Invert_A << endl ;
                } //Added
}

In the second, instead:

                SC_CTOR(inverter) {
                                 SC_METHOD(invert); //Changed
                                 sensitive << A;
                }

Hope to have good news!
SG


Il 21/02/2012 10:17, Alan Fitch ha scritto:
> On 21/02/2012 05:33, balyusuf @iastate.edu wrote:
>> Hello all,
>>
>> I added the inverter and did the unbound port, that solved the unbound
>> error I was getting. so Thanks for your help. However I am get wrong
>> results. I am trying to debug my inverter method and when I print the
>> in/out of the inverter, I always get the input and the output identical
>> (either both 0 or both 1)
>>
> Hi,
>   your inverter is working, but your print statement is "too early". The
> sc_signal class has evaluate-update semantics (delta cycle behaviour in
> VHDL terms) so when you do
>
> {
> Invert_A.write(temp);
> std::cout << "Time:" << sc_time_stamp()<< endl <<" inverter_Input : " <<
>  A << endl << " inverter_Output : " << Invert_A << endl ;
> }
>
> inside your SC_METHOD, Invert_A has not yet updated. It won't update
> until the scheduler gets to the update phase, after the SC_METHOD
> function has returned.
>
> Have a look at the section on the scheduler in the Language Reference
> Manual, or at this section on our website
>
>
http://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/
>
> or this section:
>
>
http://www.doulos.com/knowhow/systemc/tutorial/primitive_channels/
>
> regards
> Alan
>
>> here is my code for the inverter:
>>
>> //FILE: INVERTER.h
>>
>> #include <systemc.h>
>> #include <iostream>
>>
>> SC_MODULE(inverter) {
>>
>> sc_in<bool> A;
>> sc_out<bool> Invert_A;
>>
>>
>> void invert(void);
>>
>> SC_CTOR(inverter) {
>> SC_THREAD(invert);
>> sensitive << A;
>> }
>> };
>>
>>
>> //FILE:inverter.cpp
>>
>>
>> #include "inverter.h"
>> #include <iostream>
>> void inverter::invert(void) {
>>
>> bool temp = ! A.read();
>> Invert_A.write(temp);
>> std::cout << "Time:" << sc_time_stamp()<< endl <<" inverter_Input : " <<
>> A << endl << " inverter_Output : " << Invert_A << endl ;
>> }
>>
>>
>> I think I am missing something simple but I could not find it. please help!
>>
>> Thanks
>>
>> On Mon, Feb 20, 2012 at 2:35 AM, Salvatore Galfano
>> <galfanosalvatore@xxxxxxxxx <
mailto:galfanosalvatore@xxxxxxxxx>> wrote:
>>
>>     Hi,
>>
>>     this error message was gave to me when I tried to write on a port in
>>     the CTOR. In the "Creation part" port are not still working. I used
>>     the .initialize() method of the ports and then everything worked
>>     (but this is not your case). In your code I could think that the
>>     error comes from this line:
>>
>>     NotSel = !(Mux_2_Sel.read()); //you're trying to read and write a
>>     port in CTOR.
>>
>>     Try to move this statement in a separate method like
>>
>>     void inverter_method(){
>>     NotSel = !(Mux_2_Sel.read());
>>     }
>>
>>     and then in the CTOR
>>
>>     SC_METHOD(inverter_method);
>>     sensitive<<Mux_2_Sel;
>>
>>     However, if you're trying to model a mux with basic gates, I can't
>>     figure out why did not you write also a module for the simple
>>     inverter port (even if very basic it IS a port, and it should be
>>     instantiated as well as other ports in your design, in order to be
>>     coherent).
>>     Please let me know!
>>
>>     SG
>>
>>     Il 20/02/2012 09:13, 杨庆庆 ha scritto:
>>>     balyusuf @iastate.edu <
http://iastate.edu>,您好!
>>>       Well, I think "unbound" means "unconnected".
>>>     I suggest you check the source code carefully. I have met similar
>>>     errors, and generally it is because of typo error.
>>>     ======== 2012-02-20 11 <tel:2012-02-20%C2%A011>:57:56 您在来信中写
>>>     道: ========
>>>
>>>         Hi Alan,
>>>
>>>         the error message is
>>>
>>>         Error: (E112) get interface failed: port is not bound: port
>>>         'my_mux_2.port_2' (sc_in)
>>>         In file: c:\systemc-2.2.0\src\sysc\communication\sc_port.cpp:265
>>>         Press any key to continue . . .
>>>
>>>
>>>         Would you explain to me what "unbound" exactly means? I
>>>         thought I am assigning signals to all the ports, but maybe I
>>>         am doing that wrong.
>>>         In Mux_2.cpp I am assigning (Mux_2_Output = Mux_Out;) would
>>>         that be sufficient or I have to have it assigned in Mux_2.h ?
>>>
>>>         Thanks for the help,
>>>
>>>
>>>         On Sun, Feb 19, 2012 at 2:00 PM, <alan.fitch@xxxxxxxxxx
>>>         <
mailto:alan.fitch@xxxxxxxxxx>> wrote:
>>>
>>>             Hi,
>>>             it's probably best to post the error message. I would
>>>             expect it to say port_3, not port_2, as you appear to have
>>>             left the 4th port of your mux unbound (I put ****s next to
>>>             the unbound port below),
>>>
>>>             regards
>>>             Alan
>>>
>>>
>>>
>>>             -----<systemc-forum@xxxxxxxxxxxxxxxxxxx
>>>             <
mailto:systemc-forum@xxxxxxxxxxxxxxxxxxx>> wrote: -----
>>>             To: "systemc-forum@xxxxxxxxxxxxxxxxxxx
>>>             <
mailto:systemc-forum@xxxxxxxxxxxxxxxxxxx>"
>>>             <systemc-forum@xxxxxxxxxxxxxxxxxxx
>>>             <
mailto:systemc-forum@xxxxxxxxxxxxxxxxxxx>>
>>>             From: "balyusuf @iastate.edu <
http://iastate.edu>"
>>>             Sent by:
>>>             Date: 19/02/2012 19:47
>>>             Subject: [systemc-forum] HELP! "port not bound" error
>>>
>>>             Hello All,
>>>
>>>             I was able to get systemc installed on VC++. and I am
>>>             working on Mux-2:1 from "and-2" and "or_2" gates. The code
>>>             compiles and builds correctly yet I am getting a run-time
>>>             error. The error is about (my_mux_2.port_2 not bound).
>>>             Could you please help me in this with thanks in advance.
>>>
>>>
>>>             //OR_2.h
>>>             #include <systemc.h>
>>>             #include <iostream>
>>>
>>>             SC_MODULE(or_2) {
>>>
>>>             sc_in<bool> Or_A;
>>>             sc_in<bool> Or_B;
>>>             sc_out<bool> Or_Output;
>>>
>>>
>>>             void do_or(void);
>>>
>>>             SC_CTOR(or_2) {
>>>             SC_METHOD(do_or);
>>>             sensitive << Or_A << Or_B
>>>             }
>>>             };
>>>
>>>
>>>             //FILE:AND_2.h
>>>             #include <systemc.h>
>>>             #include <iostream>
>>>
>>>             SC_MODULE(and_2) {
>>>             sc_in<bool> And_A;
>>>             sc_in<bool> And_B;
>>>             sc_out<bool> And_Output;
>>>
>>>             void do_and(void);
>>>
>>>             SC_CTOR(and_2) {
>>>             SC_METHOD(do_and);
>>>             sensitive << And_A << And_B ;
>>>
>>>             }
>>>             };
>>>
>>>             //FILE:Mux_2.h
>>>             #include <systemc.h>
>>>             #include <iostream>
>>>             #include "and_2.h"
>>>             #include "or_2.h"
>>>
>>>             SC_MODULE(Mux_2) {
>>>
>>>             sc_in<bool> Mux_2_In1;
>>>             sc_in<bool> Mux_2_In2;
>>>             sc_in<bool> Mux_2_Sel;
>>>             sc_out<bool> Mux_2_Output; ********************* UNBOUND!
>>>
>>>             and_2 And_Gate1, And_Gate2, And_Gate3;
>>>             or_2 Or_Gate1, Or_Gate2;
>>>
>>>             sc_signal<bool> NotSel, A_AND_B, A_AND_NotSel, B_AND_Sel,
>>>             A_AND_NotSel_OR_A_AND_B, Mux_Out;
>>>
>>>             void Mux(void);
>>>
>>>             SC_CTOR(Mux_2): And_Gate1("And_Gate1"),
>>>             And_Gate2("And_Gate2"),
>>>             And_Gate3("And_Gate3"), Or_Gate1("Or_Gate1"),
>>>             Or_Gate2("Or_Gate2")
>>>             {
>>>             NotSel = !(Mux_2_Sel.read());
>>>             And_Gate1.And_A(Mux_2_In1); And_Gate1.And_B(Mux_2_In2);
>>>             And_Gate1.And_Output(A_AND_B);
>>>             And_Gate2.And_A(Mux_2_In1); And_Gate2.And_B(NotSel);
>>>             And_Gate2.And_Output(A_AND_NotSel);
>>>             And_Gate3.And_A(Mux_2_In2); And_Gate3.And_B(NotSel);
>>>             And_Gate3.And_Output(B_AND_Sel);
>>>
>>>             Or_Gate1.Or_A(A_AND_B); Or_Gate1.Or_B(A_AND_NotSel);
>>>             Or_Gate1.Or_Output(A_AND_NotSel_OR_A_AND_B);
>>>             Or_Gate2.Or_A(A_AND_NotSel_OR_A_AND_B);
>>>             Or_Gate2.Or_B(B_AND_Sel); Or_Gate2.Or_Output(Mux_Out);
>>>
>>>             SC_METHOD(Mux);
>>>             sensitive << Mux_2_Sel << Mux_2_In1 << Mux_2_In2;
>>>
>>>             }
>>>             };
>>>
>>>             //FILE:tb.h
>>>
>>>             #include <systemc.h>
>>>             #include <iostream>
>>>
>>>             SC_MODULE(tb) {
>>>
>>>             sc_out<bool> A, B, sel;
>>>             //sc_signal<bool> A,B,sel;
>>>
>>>             void testcases(void);
>>>
>>>             SC_CTOR(tb) {
>>>             SC_THREAD(testcases);
>>>
>>>             }
>>>             };
>>>
>>>
>>>
>>>             //FILE:or_2.cpp
>>>
>>>
>>>             #include "or_2.h"
>>>             #include <iostream>
>>>             void or_2::do_or(void) {
>>>
>>>             Or_Output.write( Or_A.read() || Or_B.read() );
>>>             std::cout << "Time:" << sc_time_stamp()<< endl <<" Fisrt
>>>             Input:" << Or_A << endl << " Second Input" << Or_B << endl
>>>             << " Output : " << Or_Output << endl ;
>>>             }
>>>
>>>             //FILE:AND_2.cpp
>>>
>>>
>>>             #include "and_2.h"
>>>             #include <iostream>
>>>             void and_2::do_and(void) {
>>>
>>>             And_Output.write(And_A.read() && And_B.read());
>>>             std::cout << "Time:" << sc_time_stamp()<< endl <<" Fisrt
>>>             Input:" << And_A << endl << " Second Input" << And_B <<
>>>             endl << " Output : " << And_Output << endl ;
>>>             }
>>>
>>>             //FILE:MUX_2.cpp
>>>
>>>             #include <iostream>
>>>             #include "Mux_2.h"
>>>
>>>             void Mux_2::Mux(void){
>>>
>>>             Mux_2_Output = Mux_Out;
>>>             std::cout << "Time:" << sc_time_stamp()<< endl <<" First
>>>             Input:" << Mux_2_In1 << endl << " Second Input" <<
>>>             Mux_2_In2 << endl << " Select Line" << Mux_2_Sel << endl
>>>             << " Output : " << Mux_2_Output << endl ;
>>>             }
>>>
>>>
>>>             #include "Mux_2.h"
>>>             #include "tb.h"
>>>             #include "tstbnsh.h"
>>>             #include <iostream>
>>>
>>>
>>>             int sc_main(int argc, char* argv[]) {
>>>
>>>             sc_signal<bool> in1, in2, sel;
>>>
>>>             tb my_tb("my_tb");
>>>             Mux_2 my_mux_2("my_mux_2");
>>>
>>>             my_mux_2.Mux_2_In1(in1);
>>>             my_mux_2.Mux_2_In2(in2);
>>>             my_mux_2.Mux_2_Sel(sel);
>>>             *********** my_mux_2.Mux_2_Output... ************** UNBOUND
>>>
>>>             my_tb.A(in1);
>>>             my_tb.B(in2);
>>>             my_tb.sel(sel);
>>>
>>>             sc_start(10, SC_SEC);
>>>             return 0;
>>>             }
>>>             //FILE:tb.cpp
>>>
>>>
>>>             #include "tb.h"
>>>             void tb::testcases(void) {
>>>
>>>             while(1)
>>>             {
>>>             A = 0;
>>>             B = 0;
>>>             sel=0;
>>>             wait(1, SC_SEC);
>>>
>>>
>>>             A = 0;
>>>             B = 1;
>>>             sel=0;
>>>             wait(1, SC_SEC);
>>>             }}
>>>
>>>
>>>             --
>>>             Alan Fitch
>>>             Senior Consultant
>>>
>>>             Doulos - Developing Design Know-how
>>>             VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl *
>>>             Tcl/Tk * Project Services
>>>
>>>             Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
>>>             Hampshire, BH24 1AW, UK
>>>             Tel: + 44 (0)1425 471223
>>>             <tel:%2B%2044%20%280%291425%20471223> Email:
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>>>            
http://www.doulos.com
>>>
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>>>
>>>             This message (and associated files) may contain
>>>             information that is confidential,
>>>             proprietary, privileged, or subject to copyright. It is
>>>             intended solely for the use
>>>             of the individual to whom it is addressed and others
>>>             authorised to receive it. If
>>>             you have received this email in error, please notify the
>>>             sender and delete all
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>>>
>>>         --
>>>         Baraa Alyusuf
>>>         Computer Engineering
>>>         Iowa State University
>>>
>>>     = = = = = = = = = = = = = = = = = = = = = =
>>>
>>>             致
>>>     礼!
>>>
>>>                   杨庆庆
>>>                    yangqingqing@xxxxxxxxxxxx
>>>     <
mailto:yangqingqing@xxxxxxxxxxxx>
>>>                    2012-02-20
>>
>>
>>
>> --
>> Baraa Alyusuf
>> Computer Engineering
>> Iowa State University
>>
>
>




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